There has been specified an MPEG2 System Standard (ISO/IEC13818-1) for packetizing the AV data, inserting calibration information (time stamp) on a reference clock into the packets, and transmitting the packets. A transport stream according to this MPEG2 System Standard is transmitted with calibration information on the reference clock such as a PCR (Program Clock Reference).
FIG. 12 is a block diagram showing a configuration of a communication system using a clock synchronization method according to a prior art, and in particular showing a clock synchronization method for a transport stream. Referring to FIG. 12, there will be described an operation according to the clock synchronization method for the transport stream. Referring to FIG. 12, the communication system is configured to include a transmitter device 71 and a receiver device 74 connected to each other via a communication line 70. The transmitter device 71 includes a PCR counter 73, and the receiver device 74 includes a PCR packet detection part 75 and a clock synchronizing part 76.
The configuration of the communication system, which uses the clock synchronization method for the transport stream and is configured as mentioned above, and an operation of the same communication system will be described below.
In addition to video packets and audio packets, the transmitter device 71 generates PCR packets periodically, and transmits the video packets, the audio packets and the PCR packets to the receiver device 74 via the communication line 70. A counted value (referred to as a PCR value hereinafter) of the PCR counter 73, which counts a transmitting clock 72, is set to each of the PCR packets. In the receiver device 74, the PCR packet detection part 75 detects the PCR packets included in the packets transmitted from the transmitter device 71, and outputs a PCR value to the clock synchronizing part 76. The clock synchronizing part 76 is configured to include a phase-locked loop (referred to as a PLL hereinafter) circuit, compares the PCR value outputted from the PCR packet detection part 75 with the PCR value counted based on a receiving clock 77, and controls the receiving clock 77 so that a difference between the both of the PCR values is smaller. By using the clock synchronization method as described above, the receiver device 74 can obtain clock signals synchronized with the transmitter device 71.
It is to be noted that Patent Documents 1 and 2, for example, show clock synchronizing circuits.    Patent Document 1: Japanese patent laid-open publication No. JP-2004-248123-A.    Patent Document 2: Japanese patent laid-open publication No. JP-2000-101560-A.